Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber

ABSTRACT

Methods for depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber are provided. The method may include: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate. Related semiconductor structures are also disclosed.

FIELD OF INVENTION

The present disclosure generally relates to methods for depositing a polysilicon film on a surface of a substrate within a reaction chamber and particularly methods for depositing a low temperature co-doped polysilicon film on a surface of a substrate by a chemical vapor deposition process.

BACKGROUND OF THE DISCLOSURE

The down scaling of semiconductor device structures, such as, for example, complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in speed and density of integrated circuits. However, conventional device scaling faces immense challenges for future technology nodes.

In the field of semiconductor device fabrication, the trend is towards a reduction in the deposition temperature of the useful layers comprising the semiconductor device, such as, for example, metal-containing layers, dielectric layers, and semiconductor layers. A reduction in the deposition temperature of useful layers may be desirable due to decreasing thermal budget requirements often necessary for the fabrication of state of the art semiconductor device structures, such as, for example, complementary metal-oxide-semiconductor (CMOS) device structures, and dynamic random access memory (DRAM) device structures. In particular semiconductor fabrication processes, high temperature deposition of useful layers may result in the unwanted thermal diffusion of materials into undesirable areas of the device structure as well as the formation of unwanted materials.

A number of semiconductor device structures may require one or more silicon layers, preferably deposited at a low deposition temperature. However, the low temperature deposition of silicon layers, e.g., below a deposition temperature of approximately 550° C., may result in silicon layers with an amorphous structure. In some semiconductor device applications, the polycrystalline form of silicon is more desirable, such as, for example, as a polycrystalline channel region of a semiconductor device structure. Accordingly, methods are desirable for enabling the low temperature deposition of polycrystalline silicon materials and particularly for the low temperature deposition of polycrystalline silicon material with p-type conductivity.

SUMMARY OF THE DISCLOSURE

In accordance with at least one embodiment of the disclosure, a method for depositing a co-doped polycrystalline film on a surface of a substrate within a reaction chamber is disclosed. The method may comprise: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, an n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate.

For the purpose of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

All of these embodiments are intended to be within the scope of the invention herein disclosed. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures, the invention not being limited to any particular embodiment(s) disclosed.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

While the specification concludes with claims particularly pointing out and distinctly claiming what are regarded as embodiments of the invention, the advantages of embodiments of the disclosure may be more readily ascertained from the description of certain examples of the embodiments of the disclosure when read in conjunction with the accompanying drawing, in which:

FIG. 1 illustrates a process flow diagram illustrating an exemplary method in accordance with the embodiments of the disclosure;

FIGS. 2A and 2B illustrate cross sectional schematic diagrams of semiconductor structures formed during an exemplary process flow in accordance with the embodiments of the disclosure; and

FIG. 3 illustrates a cross sectional schematic diagram of a semiconductor device structure which comprises a low temperature polycrystalline silicon layer deposited in accordance with the embodiments of the disclosure.

It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below.

As used herein, the term “substrate” may refer to any underlying material or materials that may be used, or upon which, a device, a circuit or a film may be formed.

As used herein, the term “chemical vapor deposition” or “CVD” may refer to a process wherein a substrate is exposed to one or more volatile precursors, which react and/or decompose on a substrate surface to produce a desired deposition. CVD processes are distinct from alternative deposition methods, such as, for example, molecular beam epitaxy (MBE), or atomic layer deposition (ALD).

As used herein, the term “polycrystalline” may refer to a material which displays short range ordering of the crystalline structure, as opposed to a “crystalline material” which displays long range ordering of the crystalline structure and as opposed to an “amorphous material” which displays substantially no ordering of the crystalline structure.

As used herein, the term “dopant precursor” may refer to a precursor comprising a dopant species which may alter the electrical characteristics of a semiconductor material by the addition of n-type carriers (n-type dopant precursor), or the addition of p-type carriers (p-type dopant precursor).

As used herein, the term “co-doped” may refer to an extrinsic semiconductor material which contains both intentionally incorporated n-type dopant species and intentionally incorporated p-type dopant species.

As used herein, the term “p-type conductivity” may refer to a semiconductor material with a majority of holes as the free charge carriers whilst electrons are the minority charge carriers.

As used herein, the term “n-type conductivity” may refer to a semiconductor material with a majority of electrons as the free charge carriers whilst holes are the minority charge carriers.

As used herein, the term “gas” or “gaseous reactant” may refer to a single gaseous reactant or a gaseous mixture composed of multiple gaseous reactants.

In the specification, it will be understood that the term “on” or “over” may be used to describe a relative location relationship. Another element or layer may be directly on the mentioned layer, or another layer (an intermediate layer) or element may be intervened therebetween, or a layer may be disposed on a mentioned layer but not completely cover a surface of the mentioned layer. Therefore, unless the term “directly” is separately used, the term “on” or “over” will be construed to be a relative concept. Similarly to this, it will be understood the term “under”, “underlying”, or “below” will be construed to be relative concepts.

The embodiments of the disclosure may include methods for depositing a semiconductor structure on a surface of a substrate and particularly methods for depositing a low temperature co-doped polysilicon semiconductor by a chemical vapor deposition process. For example, the embodiments of the disclosure may be utilized to deposit a low temperature co-doped polysilicon semiconductor material with a p-type conductivity which may have a multitude of applications in semiconductor device structures, such as, for example, as the conductive channel region in a semiconductor device structure.

Current methods for depositing polysilicon materials at reduced deposition temperatures may comprise the introduction of a silicon precursor and an n-type dopant precursor, such as, for example, a phosphorous containing dopant precursor, into a reaction chamber of a chemical vapor deposition apparatus at a deposition temperature of less than approximately 500° C. However, such deposition methods may result in polysilicon layers with n-type conductivity. In some semiconductor device structures and applications it may be advantageous to deposit polysilicon layers at a reduced deposition temperature that exhibit p-type conductivity. For example, p-type polysilicon materials may be utilized in a pn-junction semiconductor device structure, or even pnp/npn-multijunction semiconductor device structures. Accordingly, methods are desirable for depositing polysilicon at a reduced deposition temperature with p-type conductivity, whilst substantially avoiding the deposition of silicon in an amorphous crystalline state.

The embodiments of the disclosure may therefore include methods for depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber, the method comprising: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate.

The methods of the disclosure are described in greater detail with reference to FIG. 1 which comprises a process flow diagram illustrating an exemplary method 100 and with reference to FIGS. 2A and 2B which illustrate cross sectional schematic diagrams of semiconductor structures formed as part of the process flow of exemplary method 100.

The method 100 may commence with a process block 110 comprising, heating a substrate to a deposition temperature of less than 550° C. In greater detail, the process may comprise providing a substrate, such as substrate 200 of FIG. 2A. In some embodiments of the disclosure, the substrate 200 may comprise a planar substrate (as illustrated in FIG. 2A) or a patterned substrate. The substrate 200 may comprise one or more materials including, but not limited to, silicon (Si), germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), silicon germanium tin (SiGeSn), silicon carbide (SiC), or a group III-V semiconductor material, such as, for example, gallium arsenide (GaAs), gallium phosphide (GaP), or gallium nitride (GaN). In some embodiments of the disclosure, the substrate 200 may comprise an engineered substrate wherein a surface semiconductor layer is disposed over a bulk support with an intervening buried oxide (BOX) disposed there between.

Patterned substrates may comprise substrates that may include semiconductor device structures formed into or onto a surface of the substrate, for example, the patterned substrates may comprise partially fabricated semiconductor device structures, such as, for example, transistors and/or memory elements. In some embodiments, the substrate may contain monocrystalline surfaces and/or one or more secondary surfaces that may comprise a non-monocrystalline surface, such as a polycrystalline surface and/or an amorphous surface. Monocrystalline surfaces may comprise, for example, one or more of silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), or germanium (Ge). Polycrystalline or amorphous surfaces may include dielectric materials, such as oxides, oxynitrides or nitrides, such as, for example, silicon oxides and silicon nitrides.

In some embodiments of the disclosure, depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber may comprise providing the substrate to a reaction chamber of a chemical vapor deposition apparatus. For example, the substrate 200 of FIG. 2A, may be provided into a reaction chamber and the substrate may be heated to a deposition temperature within the reaction chamber. As a non-limiting example, the reaction chamber may comprise a reaction chamber of a chemical vapor deposition system.

Embodiments of the present disclosure may include deposition processes that may be performed in a chemical vapor deposition system available from ASM International N.V. under the name Intrepid™ XP or Epsilon®. However, it is also contemplated that other reaction chambers and alternative chemical vapor deposition systems from other manufacturers may also be utilized to perform the embodiments of the present disclosure.

In some embodiments of the disclosure, the substrate 200 may be heated to a desired substrate temperature within the reaction chamber of the chemical vapor deposition system. In some embodiments, depositing the co-doped polysilicon film on a surface of the substrate may comprise, heating the substrate to a temperature of less than approximately 700° C., or less than approximately 600° C., or less than approximately 550° C., or less than approximately 500° C., or less than approximately 400° C., or even less than approximately 300° C. In some embodiments, the substrate may be heated in the reaction chamber of the chemical vapor deposition apparatus to a temperature of approximately less than 550° C.

In addition to controlling the substrate temperature during the deposition process, it may be desirable to also control the pressure within the reaction chamber to a desired set point. For example, the pressure within the reaction chamber during the deposition of the polysilicon film may be less than 760 Torr, or less than 100 Torr, or even less than 10 Torr. In some embodiments of the disclosure, the pressure within the reaction chamber during the deposition of the co-doped polysilicon film may be equal to or less than approximately 100 Torr.

In some embodiments of the disclosure, once the substrate has been heated to a desired deposition temperature and the pressure in the reaction chamber has been set, one or more precursor gases may be introduced into the reaction chamber and contact the substrate 200 thereby depositing the polysilicon film over a surface of the substrate 200 via a chemical vapor deposition process, as illustrated by the semiconductor structure 204 of FIG. 2B which illustrates the substrate 200 with a polysilicon film 202 disposed over a surface of the substrate 200.

In some embodiments of the disclosure, one or more precursor gases may be introduced into the reaction chamber in order to deposit the co-doped polysilicon film 202 on a surface of the substrate 200. For example, the exemplary method 100 may continue with a process block 120 which comprises simultaneously contacting the substrate with a silicon precursor, an n-type dopant precursor, and a p-type dopant precursor. The simultaneous contacting of the substrate with a silicon precursor, an n-type dopant precursor, and a p-type dopant precursor may comprise contacting the substrate with a gaseous mixture comprising the precursor components, i.e., the precursor components concurrently interact with a surface of the substrate disposed within the reaction chamber.

In some embodiments of the disclosure, the silicon precursor may comprise at least one of silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), tetrasilane (Si₄H₁₀), isopentasilane (Si₅H₁₂), or neopentasilane (Si₅H₁₂). In some embodiments, the silicon precursor may comprise a higher order silane precursor with the general empirical formula Si_(x)H_((2x+2)). In some embodiments, the silicon precursor gas may comprise dichlorosilane (DCS). In some embodiments, the flow rate of the silicon precursor into the reaction chamber may be less than 500 sccm, or less than 250 sccm, or less than 50 sccm, or ever less than 10 sccm. In some embodiments of the disclosure, the flow rate of the silicon precursor may be approximately equal to or less than 150 sccm.

In some embodiments of the disclosure, the n-type dopant precursor may comprise at least one of phosphine (PH₃), arsine (AsH₃), tertiary butyl arsine (TBA), or tertiary butyl phosphine (TBP). In some embodiments, the flow rate of the n-type dopant precursor into the reaction chamber may be less than 1000 sccm, or less than 500 sccm, or less than 100 sccm, or ever less than 1 sccm. In some embodiments of the disclosure, the flow rate of the n-type dopant precursor may be approximately equal to or less than 50 sccm. In some embodiments, the flow rate of the n-type dopant precursor may be equal to or less than 50 sccm for a n-type dopant precursor with a dilution of less than 15% (i.e., 15% or less precursor in a diluent or carrier).

In some embodiments of the disclosure, the p-type dopant precursor may comprise at least one of diborane (B₂H₆), trimethylgallium (TMG), triethylgallium (TEG), or trimethylaluminum (TMA). In some embodiments, the flow rate of the p-type dopant precursor into the reaction chamber may be less than 10 sccm, or less than 5 sccm, or less than 1 sccm, or ever less than 0.01 sccm. In some embodiments of the disclosure, the flow rate of the p-type dopant precursor may be approximately equal to or less than 0.1 sccm. In some embodiments, the flow rate of the p-type dopant precursor may be equal to or less than 0.1 sccm for a p-type dopant precursor with a dilution of less than 1% (i.e., 1% or less precursor in a diluent or carrier).

In some embodiments, contacting the substrate with the n-type dopant precursor and the p-type dopant precursor may further comprise, introducing the n-type dopant precursor and the p-type dopant precursor into the reaction chamber at a flow rate ratio (n-type precursor flow:p-type precursor flow) of less than 10:1, or less than 5:1, or less than 2:1, or even less than 1:1. In some embodiments, the flow rate ratio, into the reaction chamber, between the n-type dopant precursor and the p-type dopant precursor may be approximately equal to or less than 5:1.

In some embodiments of the disclosure, simultaneously contacting the substrate with a silicon precursor, an n-type dopant precursor, and a p-type dopant precursor may further comprise depositing a co-doped polysilicon film on a surface of the substrate. The co-doped polysilicon film may comprise both intentionally incorporated n-type dopant species and intentionally incorporated p-type dopant species.

In some embodiments of the disclosure, the co-doped polysilicon film may comprise a p-type dopant concentration of greater than 1×10¹⁸/cm³, or greater than 1×10¹⁹/cm³, or greater than 1×10²⁰/cm³, or even greater than 1×10²¹/cm³. In some embodiments of the disclosure, the co-doped polysilicon film may comprise an n-type dopant concentration of greater than 1×10¹⁸/cm³, or greater than 1×10¹⁹/cm³, or greater than 1×10²⁰/cm³, or even greater than 1×10²¹/cm³. In some embodiments, the co-doped polysilicon film may comprise a greater concentration of p-type dopants than n-type dopants, wherein the greater concentration of p-type dopants counter dopes the n-type dopants resulting in a compensated polysilicon material. In some embodiments, the co-doped polysilicon film may have a p-type conductivity. In some embodiments, the p-type co-doped polysilicon film may have a free carrier concentration greater than 1×10¹⁶/cm³, or greater than 1×10¹⁷/cm³, or even greater than 1×10¹⁸/cm³. In some embodiments, the p-type co-doped polysilicon film may have a carrier mobility of greater than 1 cm²/Vs, or greater than 5 cm²/Vs, or even greater than 10 cm²/Vs.

In some embodiment of the disclosure, the co-doped polysilicon film 202 may be deposited to a thickness of less than 500 nanometers, or less than 250 nanometers, or less than 100 nanometer, or less than 50 nanometers, or less than 25 nanometers, or less than 10 nanometers, or less than 5 nanometers, or even less than 1 nanometer.

The methods and semiconductor structures disclosed herein may be utilized in a number of semiconductor device applications. As a non-limiting example embodiment of the current disclosure, FIG. 3 illustrates a partially fabricated semiconductor device structure 300 which may comprise, a partially fabricated memory element, such as, a vertical NAND memory element. In more detail, partially fabricated semiconductor device structure 300 may comprise a substrate 302 (e.g., bulk silicon) and disposed over the substrate 302 may be alternating layers of silicon oxide 304 and silicon nitride 306. Disposed on a surface of the silicon nitride layers 306 and the silicon oxide layers 304 is one or more p-type co-doped polysilicon layers 308 deposited utilizing the embodiments disclosed herein. Finally, the partially fabricated semiconductor device structure 300 may comprise a silicon dioxide (SiO₂) layer 310 disposed on the one or more p-type polysilicon layers 308.

Low temperature chemical vapor deposition of crystalline silicon containing films may be difficult beyond a thickness of greater than approximately 10 nanometers-20 nanometers, wherein the crystalline silicon may pass through the crystalline-to-amorphous transition, resulting in an undesirable amorphous crystalline silicon material. For example, silicon containing films deposited at a temperature between approximately 300° C.−600° C. may become amorphous above a thickness between approximately 10 nanometers-20 nanometers. It is therefore desirable to deposit crystalline silicon material at a reduced temperature, e.g., below approximately 600° C., whilst maintaining the crystallinity of the silicon above a thickness of approximately 20 nanometers. Not to be bound by any theory, it is believed that one cause for the crystalline-to-amorphous transition observed in silicon films may be due to the accumulation of hydrogen in the silicon film, leading to an increased stress in the film that may eventually lead to an amorphous silicon deposition above a critical thickness. Again, not to be bound by any theory, but it is believed that the removal of excess hydrogen during the deposition of the crystalline silicon would reduce the buildup of stress in the crystalline silicon film and thereby prevent the transition from crystalline to amorphous deposition of the silicon film. Methods are therefore desirable for low temperature deposition of crystalline silicon containing films, e.g., below a temperature of approximately 600° C., while maintaining the crystalline structure of the silicon film.

In some embodiments of the disclosure, methods for depositing crystalline silicon containing films at low temperature via chemical vapor deposition are provided. For example, the methods of deposition may comprise providing a substrate and heating said substrate to a temperature between approximately 350° C. and approximately 600° C., wherein the substrate is disposed within a reaction chamber of a chemical vapor deposition apparatus. In some embodiments, the pressure in the reaction chamber may be set to less than 760 Torr, or less than 100 Torr, or even less than 10 Torr. In some embodiments of the disclosure, the pressure within the reaction chamber during the deposition of the crystalline silicon film may be equal to or less than approximately 1 Torr.

In some embodiments of the disclosure, upon heating the substrate and setting the pressure within the reaction chamber to desired set points, the substrate may be contacted with one or more precursor gases to deposit the crystalline silicon containing film. In some embodiments, the substrate may be contact with one or more silicon precursors and one or more germanium precursors. In some embodiments, the silicon precursor may be continuous supplied to the reaction chamber to contact the substrate and the germanium precursor may be continuously supplied to the reaction chamber to contact the substrate. In alternative embodiments, the silicon precursor may be continuously supplied to the reaction chamber to contact the substrate and the germanium precursor may be pulsed at specific intervals, e.g., regularly timed intervals, into the reaction chamber and contact the substrate disposed therein.

In some embodiments, the silicon precursor may comprise silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), tetrasilane (Si₄H₁₀), isopentasilane (Si₅H₁₂), or neopentasilane (Si₅H₁₂). In some embodiments, the silicon precursor may comprise a higher order silane precursor with the general empirical formula Si_(x)H_((2x+2)). In some embodiments, the silicon precursor gas may comprise dichlorosilane (DCS). As a non-limiting example, the silicon precursor may comprise trisilane (Si₃H₈) and may be introduced into the reaction chamber at flow rate between approximately 5 sccm to 150 sccm.

In some embodiments of the disclosure, the one or more germanium precursors may comprise at least one of germane (GeH₄), digermane (Ge₂H₆), trigermane (Ge₃H₈), or germylsilane (GeH₆Si). In some embodiments, the germanium precursor may comprise a Si—Ge-hydride precursor, such as, (H₃Ge)_(x)SiH_(4−x), wherein x=1-4, or (H₃Si)_(x)GeH_(4−x), where x—1-4. In some embodiments, the flow rate of the germanium precursor may be less than 500 sccm, or less than 200 sccm, or less than 50 sccm, or less than 10 sccm, or even less than 5 sccm. As a non-limiting example, the germanium precursor may comprise germane (GeH₄) (10% diluted, i.e., 10% precursor in a carrier), wherein the germane is introduced into the reaction chamber at flow rate between approximately 5 sccm and approximately 500 sccm.

The silicon precursor and germanium precursor may contact the heated substrate within the chemical vapor deposition apparatus and deposit a crystalline silicon containing film. In some embodiments, the germanium precursor may introduce a small quantity of germanium into the crystalline silicon containing film. For example, the crystalline silicon containing film may comprise between approximately 0.1% to approximately 4% germanium.

The embodiments of the disclosure, therefore allow for the low temperature deposition of a crystalline silicon containing film at a thickness of greater than 10 nanometers, or greater than 20 nanometers, or greater than 100 nanometers, or even greater than 200 nanometers, wherein the crystalline silicon containing film is substantially free of amorphous material.

The example embodiments of the disclosure described above do not limit the scope of the invention, since these embodiments are merely examples of the embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternative useful combination of the elements described, may become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims. 

What is claimed is:
 1. A method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber, the method comprising: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate, wherein the deposited co-doped polysilicon film has a p-type dopant concentration greater than 1×10¹⁸/cm³ and an n-type dopant concentration greater than 1×10¹⁸/cm³.
 2. The method of claim 1, wherein the silicon precursor comprises at least one of silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), or tetrasilane (Si₄H₁₀).
 3. The method of claim 1, wherein the n-type dopant precursor comprises at least one of phosphine (PH₃), arsine (AsH₃), tertiary butyl arsine (TBA), or tertiary butyl phosphine (TBP).
 4. The method of claim 1, wherein the p-type dopant precursor comprises at least one of diborane (B₂H₆), trimethylgallium (TMG), triethylgallium (TEG), or trimethylaluminum (TMA).
 5. The method of claim 1, wherein the co-doped polysilicon film has p-type conductivity.
 6. The method of claim 1, wherein contacting the substrate with the silicon precursor further comprises introducing the silicon precursor into the reaction chamber at a flow greater than 10 sccm.
 7. The method of claim 1, wherein contacting the substrate with the n-type dopant precursor further comprises introducing the n-type dopant precursor into the reaction chamber at a flow rate greater than 1 sccm.
 8. The method of claim 1, wherein contacting the substrate with the p-type dopant precursor further comprises introducing the p-type dopant precursor into the reaction chamber at a flow rate greater than 0.01 sccm.
 9. The method of claim 1, wherein the contacting the substrate with the n-type dopant precursor and the p-type dopant precursor further comprises introducing the n-type dopant precursor and the p-type dopant precursor into the reaction chamber at a flow rate ratio of approximately less than 5:1.
 10. The method of claim 1, wherein the pressure within the reaction chamber is less than 100 Torr.
 11. The method of claim 1, wherein the polysilicon film is deposited by a chemical vapor deposition process.
 12. A semiconductor device structure comprising the co-doped polysilicon film deposited by the method of claim
 1. 